| From: | Peter Geoghegan <pg(at)heroku(dot)com> |
|---|---|
| To: | Andres Freund <andres(at)2ndquadrant(dot)com> |
| Cc: | Greg Stark <stark(at)mit(dot)edu>, Tom Lane <tgl(at)sss(dot)pgh(dot)pa(dot)us>, PostgreSQL-development <pgsql-hackers(at)postgresql(dot)org> |
| Subject: | Re: Misaligned BufferDescriptors causing major performance problems on AMD |
| Date: | 2014-02-05 18:13:40 |
| Message-ID: | CAM3SWZSEXRSwJw=18CyBmOC5vt_kbEkoowEg2CRQzEH+tgMMrw@mail.gmail.com |
| Views: | Raw Message | Whole Thread | Download mbox | Resend email |
| Thread: | |
| Lists: | pgsql-hackers |
On Wed, Feb 5, 2014 at 7:21 AM, Andres Freund <andres(at)2ndquadrant(dot)com> wrote:
> All current x86 processors use 64. But even if it were bigger/smaller,
> they will be either 32, or 128. Neither benefits from touching more
> cachelines than necessary. E.g. in the 128 case, we could still touch
> two with the current code.
That's true, but I believe that a hardware optimization called
Adjacent Cache Line Prefetch is widely supported by recent
microarchitectures, and is sometimes enabled by default. I'm not
suggesting that that would necessarily radically alter the outcome,
but it is a consideration.
--
Peter Geoghegan
| From | Date | Subject | |
|---|---|---|---|
| Next Message | Tom Lane | 2014-02-05 18:21:58 | Re: Patch: show xid and xmin in pg_stat_activity and pg_stat_replication |
| Previous Message | Andrew Dunstan | 2014-02-05 18:10:50 | Re: jsonb and nested hstore |