Re: Latches with weak memory ordering (Re: max_wal_senders must die)

On Fri, Nov 19, 2010 at 9:31 AM, Robert Haas <robertmhaas(at)gmail(dot)com> wrote:

>> Just a small point of clarification - you need to have both that
>> unknown archtecture, and that architecture has to have postgres
>> process running simultaneously on difference CPUs with different
>> caches that are incoherent to have those problems.
>
> Sure you do.  But so what?  Are you going to compile PostgreSQL and
> implement TAS as a simple store and read-fence as a simple load?  How
> likely is that to work out well?

If I was trying to "port" PostgreSQL to some strange architecture, and
my strange architecture didtt' have all the normal TAS and memory
bariers stuff because it was only a UP system with no cache, then yes,
and it would work out well ;-)

If it was some strange SMP architecture, I wouldn't expect *anything*
to work out well if the architecture doesn't have some sort of
TAS/memory barrier/cache-coherency stuff in it ;-)

a.

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