Asynchronous DRAM Self-Refresh

Hackers,

At CoreOS Fest, Intel presented about a technology which they used to
improve write times for the nonrelational data store Etcd. It's called
Asynchronous DRAM Self-Refresh, or ADR. This is supposedly a feature of
all of their chips since E5 which allows users to designate a small area
of memory (16 to 64MB) which is somehow guaranteed to be flushed to disk
in the event of a power loss (the exact mechanism was not explained).

So my thought was "Hello! wal_buffers?" Theoretically, this feature
could give us the benefits of aynchronous commit without the penalties
... *if* it actually works.

However, since then I've been able to find zero documentation on ADR.
There's a bunch of stuff in the Intel press releases, but zero I can
find in their technical docs. Anyone have a clue on this?

--
Josh Berkus
PostgreSQL Experts Inc.
http://pgexperts.com