Re: Latches with weak memory ordering (Re: max_wal_senders must die)

From: Markus Wanner <markus(at)bluegap(dot)ch>
To: Tom Lane <tgl(at)sss(dot)pgh(dot)pa(dot)us>
Cc: Aidan Van Dyk <aidan(at)highrise(dot)ca>, Andres Freund <andres(at)anarazel(dot)de>, Robert Haas <robertmhaas(at)gmail(dot)com>, pgsql-hackers(at)postgresql(dot)org, Heikki Linnakangas <heikki(dot)linnakangas(at)enterprisedb(dot)com>, Bruce Momjian <bruce(at)momjian(dot)us>, Josh Berkus <josh(at)agliodbs(dot)com>
Subject: Re: Latches with weak memory ordering (Re: max_wal_senders must die)
Date: 2010-11-19 16:14:55
Message-ID: 4CE6A27F.60003@bluegap.ch
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On 11/19/2010 04:51 PM, Tom Lane wrote:
> Hm, what do those do exactly?

"Performs a serializing operation on all load-from-memory and
store-to-memory instructions that were issued prior the MFENCE
instruction." [1]

Given the memory ordering guarantees of x86, this instruction might only
be relevant for SMP systems, though.

> Or does "lock xchgb" imply an mfence?

Probably on older architectures (given the name "bus locked exchange"),
but OTOH I wouldn't bet on that still being true. Locking the entire bus
sounds like a prohibitively expensive operation with today's amounts of
cores per system.

Regards

Markus Wanner

[1]: random google hit on 'mfence':
http://siyobik.info/index.php?module=x86&id=170

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