From: | Tom Lane <tgl(at)sss(dot)pgh(dot)pa(dot)us> |
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To: | Greg Stark <gsstark(at)mit(dot)edu> |
Cc: | pgsql-hackers(at)postgresql(dot)org, "Sergey E(dot) Koposov" <math(at)sai(dot)msu(dot)ru> |
Subject: | Re: IA64 versus effective stack limit |
Date: | 2010-11-06 21:15:16 |
Message-ID: | 25027.1289078116@sss.pgh.pa.us |
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Lists: | pgsql-hackers |
Greg Stark <gsstark(at)mit(dot)edu> writes:
> On Sat, Nov 6, 2010 at 5:34 PM, Tom Lane <tgl(at)sss(dot)pgh(dot)pa(dot)us> wrote:
>> As I said above, I don't know of any good way to measure register stack
>> depth directly. It's probably possible to find out by asking the kernel
>> or something like that, but we surely do not want to introduce a kernel
>> call into check_stack_depth().
> It seems more likely it would be some kind of asm than a trap. This
> might be wishful thinking but is it too much to hope that glibc
> already exposes it through some function?
Yeah, I suppose some asm might be a possible solution, but I was a bit
discouraged after reading some Intel documentation that said that the
register-stack top wasn't exposed in the architectural model. You
apparently can only find out what's been spilled to memory. (But
perhaps that's close enough, for the purposes here?)
regards, tom lane
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