Re: Misaligned BufferDescriptors causing major performance problems on AMD

On 2015-01-28 10:35:28 -0500, Tom Lane wrote:
> Andres Freund <andres(at)2ndquadrant(dot)com> writes:
> > On 2015-01-26 21:13:31 -0500, Robert Haas wrote:
> >> So maybe we should also do something like what LWLocks do, and make a
> >> union between the actual structure and an appropriate array of padding
> >> bytes - say either 64 or 128 of them.
>
> > Hm. That's a bit bigger patch. I'm inclined to just let it slide for the
> > moment. I still have plans to downsize some of sbufdesc's content (move
> > the io lock out) and move the content lwlock inline. Then we're not
> > going to have much choice but do this...
>
> Even if you didn't have plans like that, it would be entire folly to
> imagine that buffer headers will be exactly 64 bytes without some forcing
> function for that.

Meh. The 128 byte additionally used by the alignment don't hurt in any
case. But forcing all buffer descriptors to 64bit on a 32bit platform
isn't guaranteed to be performance neutral.

So, no I don't think it's a "folly" to do so.

I'd rather make actual progress that improves the absurd situation today
(a factor of 2-3 by changing max_connections by one...) than argue
whether the impact on 32bit platforms is acceptable before doing so. If
we additionally decide to pad the struct, fine. But I don't see why this
has to be done at the same time.

Greetings,

Andres Freund

--
Andres Freund http://www.2ndQuadrant.com/
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