| From: | Andres Freund <andres(at)anarazel(dot)de> |
|---|---|
| To: | pgsql-hackers(at)postgresql(dot)org |
| Cc: | Tom Lane <tgl(at)sss(dot)pgh(dot)pa(dot)us>, Markus Wanner <markus(at)bluegap(dot)ch>, Aidan Van Dyk <aidan(at)highrise(dot)ca>, Robert Haas <robertmhaas(at)gmail(dot)com>, Heikki Linnakangas <heikki(dot)linnakangas(at)enterprisedb(dot)com>, Bruce Momjian <bruce(at)momjian(dot)us>, Josh Berkus <josh(at)agliodbs(dot)com> |
| Subject: | Re: Latches with weak memory ordering (Re: max_wal_senders must die) |
| Date: | 2010-11-19 23:57:38 |
| Message-ID: | 201011200057.39258.andres@anarazel.de |
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On Saturday 20 November 2010 00:08:07 Tom Lane wrote:
> Andres Freund <andres(at)anarazel(dot)de> writes:
> > On Friday 19 November 2010 18:46:00 Tom Lane wrote:
> >> I poked around in the Intel manuals a bit. They do have mfence (also
> >> lfence and sfence) but so far as I can tell, those are only used to
> >> manage loads and stores that are issued by special instructions that
> >> explicitly mark the operation as weakly ordered. So the reason we're
> >> not seeing bugs is presumably that C compilers don't generate such
> >> instructions.
> >
> > Well. Some memcpy() implementations use string (or SIMD) operations which
> > are weakly ordered though.
> Like it says, the cache coherency mechanism prevents this from being a
> problem for us. Once the change is made in a processor's cache, it's
> the cache's job to ensure that all processors see it --- and on Intel
> architectures, the cache does take care of that.
Check example 8.2.3.4 of 3a. - in my opinion that makes my example correct.
Andres
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