Re: Proposal: Removing 32 bit support starting from PG17++

Thomas Munro <thomas(dot)munro(at)gmail(dot)com> writes:
> On Thu, May 25, 2023 at 11:51 AM Tom Lane <tgl(at)sss(dot)pgh(dot)pa(dot)us> wrote:
>> You'll no doubt be glad to hear that I'll be retiring chickadee
>> in the very near future.

> . o O { I guess chickadee might have been OK anyway, along with e.g.
> antique low-end SGI MIPS gear etc of "workstation"/"desktop" form that
> any collector is likely to have still running, because they only had
> one CPU (unlike their Vogon-spaceship-sized siblings). As long as
> they had 64 bit load/store instructions, those couldn't be 'divided'
> by an interrupt, so scheduler switches shouldn't be able to tear them,
> AFAIK? }

PA-RISC can probably do tear-free 8-byte reads, but Andres also
wanted to raise the bar enough to include 32-bit atomic instructions,
which PA-RISC hasn't got; the one such instruction it has is
limited enough that you can't do much beyond building a spinlock.

Dunno about antique MIPS. I think there's still some interest in
not-antique 32-bit MIPS; I have some current-production routers
with such CPUs. (Sadly, they don't have enough storage to do
anything useful with, or I'd think about repurposing one for
buildfarm.)

regards, tom lane